Reference is made to FIG. 1 showing a cross-section view of an embodiment of a cell 10 of an image sensor as taught by U.S. Pat. No. 8,513,761 (incorporated by reference). This cell 10 is manufactured from a portion of a semiconductor layer (or body) 12 that is lightly-doped with a first conductivity type dopant. The semiconductor material for layer 12 may, for example, comprise silicon. The dopant concentration within layer 12 may, for example, be on the order of from 1014 to 1016 atoms/cm3. The layer 12 has a thickness smaller than 20 preferably on the order of from 2 to 6 μm and may, for example, have been formed as the upper silicon layer of a structure of silicon on insulator type (SOI). A wall 14 surrounds the cell 10 and separates the cell 10 from neighboring cells in the image sensor (with a pitch, for example, for adjacent cells of 2 μm). The wall 14 comprises a capacitive deep trench isolation (CDTI) type structure that is formed by a trench 16 having an insulating liner 18 (such as formed by a thermal oxide) and filled with a conductive or semiconductive material (such as a polysilicon material) 20. The trench 16 extends completely through the thickness of the layer 12. The material 20 is electrically connected to be biased with a voltage Vwall. A width of the wall 14 may, for example, be 0.2-0.4 μm. The width of the cell 10 may, for example, be on the order of about 2 μm.
At a front side of the layer 12, a ring shaped well 22 heavily-doped with a second conductivity type dopant extends into the layer 12. The dopant concentration within well 22 may, for example, be on the order of from 1×1016 to 1×1018 atoms/cm3. A lateral width of ring well may, for example, be 0.5-0.6 μm. The ring shaped well 22 surrounds a central first conductivity type region of the layer 12 at the front side. The central first conductivity type region includes a portion 24 of the lightly-doped layer 12 and a top region 26 heavily-doped with the first conductivity type dopant and extending into the layer 12 on top of and in contact with the portion 24. The dopant concentration within top region 26 may, for example, be on the order of from 1×1019 to 5×1020 atoms/cm3. A lateral width of the central first conductivity type top region 26 may, for example, be 0.2-0.6 μm.
The central first conductivity type top region 26 is separated from the ring shaped well 22 by a wall 30. A width of the wall 30 may, for example, be 0.1-0.4 μm. The wall 30 comprises a vertical gate (VEGA) electrode type structure that is formed by a trench 32 having an insulating liner 34 (such as formed by a thermal oxide) and filled with a semiconductive material (such as a polysilicon material) 36. The trench 32 extends to a depth that exceeds the thickness of the ring shaped well 22 (but does not extend completely through the layer 12). The material 36 is electrically connected to be biased with a voltage Vgate. The portion 24, top region 26 and VEGA electrode form a transfer gate transistor (TG) for the cell 10. The ring shaped well 22 supports the formation of a number of other transistors of the planar MOSFET type for the cell 10. These transistors include a reset (precharge) transistor (RST) and a source-follower transistor (SF). The connection and operation of the transistors TG, RST and SF are well known to those skilled in the art with respect to the operation of the cell 10. A read transistor for the cell 10 is not shown in FIG. 1 but is connected to the circuitry in a manner known to those skilled in the art to support signal read out operations. In general, various metallization levels are formed on the front side to ensure the electrical connections to and between the drains, sources, and gates of the various transistors. In particular, an interconnect corresponding to a read node S of the cell is provided between top region 26, the drain of reset transistor RST, and the gate of the source-follower transistor SF is supported by the various metallization levels. The precharge and read transistors may be common to several neighboring cells (for example, shared by a group of four cells).
The cell 10 is a backside illumination (BSI) device. At a back side of the layer 12, a thin layer 40 heavily-doped of the second conductivity type is formed extending into the layer 12 from the rear surface. The dopant concentration within layer 40 may, for example, be on the order of from 1×1017 to 1×1019 atoms/cm3. The layer 40 has a function of inversion of the type of majority carriers contained in layer 12. This inversion of the concentration of the type of carriers might also be performed by a MOS capacitance at the rear surface provided with an electrode (metallic, semiconductor, or dielectric), transparent in the useful sensor sensitivity spectrum, which creates a free carrier inversion channel (MOS effect).
The rear surface of each cell is covered with an antireflection coating layer 42 and a filter layer 44 having the desired color for the considered cell, for example, red, green, blue or infra-red. Although this is optional in this type of structure, a lens 48 may cover filter layer 44.
Operation of the cell for light detection is well known in the art. There is a phase of photoconversion or integration during which the rear surface is illuminated and electrons are stored in a charge collection area of layer 12. A transfer phase then occurs during which the electrons are transferred from a charge collection area of layer 12 to the top region 26 working as the read node S. During the integration phase, the conduction between the charge collection area of layer 12 and top region 26 is interrupted by the transfer gate transistor (TG) in response to application of the gate voltage Vgate to the conductor 36 of the vertical gate electrode. When the vertical gate electrode is biased at a low or negative voltage, for example, −1 volt, the portion 24 of the lightly-doped layer 12 is fully depleted from electrons and the passing of the charge carriers is inhibited by the potential barrier (inversion layer) thus created between portion 24 and the charge collection area of layer 12. Thus, the portion 24 plays the role of a controlled channel region and top region 26 corresponds to a drain region of the transfer gate transistor connected to the read node S.